Electronic devices having integrated reset systems and methods thereof

ABSTRACT

Methods and devices for power cycling an electronic device are provided. Also provided are systems and kits.

RELATED APPLICATION

The present application claims priority to provisional application No.61/553,942 filed Oct. 31, 2011, entitled “Electronic Devices HavingIntegrated Reset Systems and Methods Thereof”, the disclosure of whichis incorporated herein by reference for all purposes.

BACKGROUND

In using electronic devices, such as computers, smart phones, PDAs,etc., a user may experience a situation in which the electronic device“hangs” or “crashes”. A hang, sometimes referred to as a “freeze”,occurs when the device ceases to respond to inputs. In the most commonlyencountered scenario, the device's display becomes static and isunresponsive to any user input, e.g., clicking or movement of a mousecursor, typing on a keyboard, or touching a touch screen, etc. Manymodern operating systems provide the user with a means to terminate ahung program or device without rebooting or power cycling the device. Inmore severe hangs, however, the device may have to be power cycled,which is often accomplished with an on/off or reset button provided onthe device. A crash, on the other hand, is a condition in which theelectronic device or a program, either an application or part of theoperating system, ceases to function properly, often exiting afterencountering errors. This is different from a hang or freeze where theapplication or operating system continues to run without obviousresponse to input.

Often, the only way to recover from a hang or crash is to reboot orreset the device, usually by turning it off and then on again—calledpower cycling. Power cycling typically involves resetting or clearingany pending errors or events and then bringing the system to normalconditions or to an initial or default state in a controlled manner.Depending on the device configuration, a device may be able toautomatically reset itself by means of an internal program which istriggered if a command times out. However, such a timing out does notalways occur or is too lengthy, and even if pending, a user often has noway of knowing if and when the reset will happen. As such, mostconventional electronic devices have a means to enable a user action formanually initiating a reset. One such common means is a reset button,the location of which is not always obvious (e.g., it may be recessedwithin the device housing) and may require an extra tool (e.g.,paperclip or the like) to access. Alternatively, the power cycling orreset may require simultaneously or serially pressing or holding adesignated combination of keys (e.g., user interface keys), thecombination of which may be unknown or not readily available to a user.Other ways in which a device can be configured to be reset is byprolonged removal of the battery or batteries or by installing thebatteries upside down (i.e., the positive side of the battery isconnected to the positive contact in the battery receptacle, and thesame for the negative). Often, these actions are neither obvious noreffortless for users, require extra electro-mechanical hardware and/orrequire additional device housing access points, all of which add to thecost of the device and increase the risk of electrostatic discharge(ESD) and liquid ingress issues.

Accordingly, it would be desirable and beneficial to provide means andmethods of resetting or power cycling electronic devices which overcomethe disadvantages of the prior art.

SUMMARY

Certain embodiments of the present disclosure include power cycling anelectronic device having a data processor, enabling a reset circuit toprovide a reset signal to the data processor, supplying power to thedata processor while enabling the reset circuit, disabling the resetcircuit while maintaining power to the data processor, enabling thereset circuit while maintaining power to the data processor, andremoving power to the data processor while enabling the reset circuit.

Certain embodiments include a device housing that encases power cyclingelectronic components of the electronic device including a printedcircuit board, a data processor, a power interface circuit that providesat least one power input line to the data processor, a reset circuitthat provides a reset signal to the data processor via a reset line, abattery receptacle terminal configured to receive a battery packincluding at least one cathode terminal, at least one anode terminal,and at least one reset pad electrically coupled to an input of the resetcircuit, and a battery pack including a housing and at least one batteryretained in the housing and positioned between at least one batterybetween the at least one cathode terminal and the at least one anodeterminal, the battery configured as the supply voltage of the electronicdevice, wherein the reset circuit includes a reset switch positionedbetween the reset circuit and system ground.

Certain embodiments include power cycling an electronic device having adata processor including receiving an electrical short from at least onebattery, receiving a first voltage input signal from one or more resetlines that is HI, receiving a second voltage input signal from one ormore power lines that is LO, receiving a third voltage input signal fromthe one or more power lines that is HI, determining that the firstvoltage input signal from the one or more reset lines remains HI,receiving a fourth voltage input signal from the one or more reset linesthat is LO, and determining that the third voltage input signal from theone or more power lines remains HI.

These and other embodiments, objects, advantages, and features of thedisclosure will become apparent to those persons skilled in the art uponreading the details of exemplary embodiments of the disclosure as morefully described below.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present disclosure are best understood from thefollowing detailed description when read in conjunction with theaccompanying drawings. It is emphasized that, according to commonpractice, the various features of the drawings are not to scale. On thecontrary, the dimensions of the various features are arbitrarilyexpanded or reduced for clarity. Included in the drawings are thefollowing figures:

FIG. 1 is a block diagram of a portion of a device's electronicsincluding power cycling and/or reset circuitry of one or moreembodiments of the present disclosure;

FIGS. 2A and 2B are top and side cutaway views, respectively, of certainstructural embodiments of an electronic device having a configurationfor power cycling and/or reset upon battery insertion into and/orremoval from the device;

FIG. 2C is an enlarged view of the area noted in FIG. 2B;

FIGS. 3A and 3B are top and side cutaway views of the device of FIGS. 2Aand 2B in a first stage of battery insertion (or, in reverse sequence, athird stage of battery removal) for implementing a power cycling orreset procedure of certain embodiments of the present disclosure;

FIGS. 4A and 4B are top and side cutaway views of the device of FIGS. 2Aand 2B in a second stage of battery insertion (or, in reverse sequence,a second stage of battery removal) for implementing a power cycling orreset procedure of certain embodiments of the present disclosure;

FIGS. 5A and 5B are top and side cutaway views of the device of FIGS. 2Aand 2B in a final stage of battery insertion (or, in reverse sequence, afirst stage of battery removal) for implementing a power cycling orreset procedure of certain embodiments of the present disclosure; and

FIGS. 6A and 6B are graphs showing the status of the reset and powerlines, respectively, of the device of FIGS. 2A and 2B during the variousstages of battery insertion/removal of FIGS. 3A/3B, 4A/4B and 5A/5B.

DETAILED DESCRIPTION

Before the present disclosure is further described, it is to beunderstood that this disclosure is not limited to particular embodimentsdescribed, as such may, of course, vary. It is also to be understoodthat the terminology used herein is for the purpose of describingparticular embodiments only, and is not intended to be limiting, sincethe scope of the present disclosure will be limited only by the appendedclaims.

As will be apparent to those of skill in the art upon reading thisdisclosure, each of the individual embodiments described and illustratedherein has discrete components and features which may be readilyseparated from or combined with the features of any of the other severalembodiments without departing from the scope or spirit of the presentdisclosure.

Where a range of values is provided, it is understood that eachintervening value, to the tenth of the unit of the lower limit unlessthe context clearly dictates otherwise, between the upper and lowerlimit of that range and any other stated or intervening value in thatstated range, is encompassed within the disclosure. The upper and lowerlimits of these smaller ranges may independently be included in thesmaller ranges, and are also encompassed within the disclosure, subjectto any specifically excluded limit in the stated range. Where the statedrange includes one or both of the limits, ranges excluding either orboth of those included limits are also included in the disclosure.

Unless defined otherwise, all technical and scientific terms used hereinhave the same meaning as commonly understood by one of ordinary skill inthe art to which this disclosure belongs. Although any methods andmaterials similar or equivalent to those described herein can also beused in the practice or testing of the present disclosure, exemplarymethods and materials are now described. All publications mentionedherein are incorporated herein by reference to disclose and describe themethods and/or materials in connection with which the publications arecited.

As used herein and in the appended claims, the singular forms “a,” “an,”and “the” include plural referents unless the context clearly dictatesotherwise. It is further noted that the claims may be drafted to excludeany optional element. As such, this statement is intended to serve asantecedent basis for use of such exclusive terminology as “solely,”“only” and the like in connection with the recitation of claim elements,or use of a “negative” limitation.

The publications discussed herein are provided solely for theirdisclosure prior to the filing date of the present application. Nothingherein is to be construed as an admission that the present disclosure isnot entitled to antedate such publication by virtue of prior disclosure.Further, the dates of publication provided may be different from theactual publication dates which may need to be independently confirmed.

While the present disclosure has been described with reference to thespecific embodiments, it should be understood by those skilled in theart that various changes may be made and equivalents may be substitutedwithout departing from the true spirit and scope of the disclosure. Inaddition, many modifications may be made to adapt a particularsituation, material, composition of matter, process, process step orsteps, to the objective, spirit and scope of the present disclosure. Allsuch modifications are intended to be within the scope of the claimsappended hereto.

Referring now to FIG. 1, there is shown a block diagram 10 of a portionof the electronics of a battery-powered electronic device including thepower cycling/reset electronics in certain embodiments of the presentdisclosure. The electronic device may include, but is not limited to,for example, a blood glucose meter, a continuous glucose monitoringdevice, or an infusion device such as an insulin pump. The electronicdevice includes a data processor or microprocessor 20, which, in certainembodiments, is provided along with other integrated circuits (notshown) on a printed circuit board (PCB), for performing the device'sdata processing and/or data communication (i.e., data transmission andreception) functions. The device electronics further include circuitryfor providing and regulating the supply of voltage to the various devicecomponents including data processor 20. Such circuitry includes a powerinterface circuit 30 which provides one or more power input lines 50 todata processor 20, and a source of power 40, i.e., one or morereplaceable batteries described in greater detail below, positionedbetween power interface circuit 30 and system ground. Power interfacecircuit 30 may include a backup battery and/or one or more largecapacitors which maintain power to data processor 20 and certain othercircuits, e.g., a memory, in case of a loss of primary power 40, such aswhen the battery is being replaced or expires prior to replacement.

Referring still to FIG. 1, the power reset circuitry in certainembodiments of the present disclosure, which works cooperatively withthe power components described above, includes a reset circuit 60 whichprovides a reset signal to data processor 20 via reset line 80. Thepower reset circuitry also includes a reset switch 70 positioned betweenreset circuit 60 and system ground. Reset switch 70, in certainembodiments, is structurally provided by a pair of contacts 110 a, 110 bwhich are, as shown in FIGS. 2A-2C, in certain embodiments, positionedside-by-side and marginally spaced apart from a front or distal side orend 106 a of a battery contact pad 106, which is schematicallyrepresented in FIG. 1 by the negative terminal (or the positive terminaldepending on the desired orientation) of battery 40. When a conductor isextended between contact points 110 a and 110 b, reset switch 70 isclosed thereby grounding reset circuit 60 which in turn sends a resetsignal via line 80 to data processor 20. Conversely, when the contactpoints are not electrically connected, reset switch 70 is open with noreset signal being provided by reset circuit 60 to data processor 20.

Referring now to FIGS. 2A-2C, an electronic device 100 is shown having,in certain embodiments, a device housing 102 which encases the device'selectronic components, many of which are provided on PCB 104, includingthe circuitry of FIG. 1 as well as opposing, spaced apart batteryreceptacle contacts or terminals 106, 108 configured for receiving areplaceable battery therebetween. While a single replaceable battery maybe employed as the system's supply voltage, the illustrated deviceembodiment is configured to operate with a battery pack 120 including apair of batteries 114 retained within an insulated housing or tray 122,which is shaped and configured to mate in sliding or snap-fit engagementwith a distal or receiving end of device housing 102. When fully engagedwith each other, the combined housings 102, 122 may provide ahermetically resistant seal about the device. If used, a battery pack,in certain embodiments, includes two replaceable batteries of the samesize that are held and positioned in tandem. Although any suitablebattery type may be used depending on the subject electronic device,common battery types for providing a long service life, i.e., typicallywell over a year of continuous use, for small portable or hand-heldelectronic devices include but are not limited to coin or button cellbatteries. In such batteries, the can 118 typically functions as theanode or positive terminal and the cap 116 typically functions as thecathode or negative terminal. Suitable anode materials include but arenot limited to zinc and lithium, and suitable cathode materials includebut are not limited to manganese dioxide, silver oxide, carbonmonofluoride, cupric oxide and oxygen from the air. By way of example, astandard lithium battery, such as the CR2032 battery, which is rated at3.0 V, can be used in the presently disclosed device. Referring again toFIGS. 2A-2C, each pair of battery receptacle terminals includes acathode or negative terminal 106 and an anode or positive terminal 108.Each negative terminal 106 is in the form of a conductive pad having ashape corresponding to that of the can 118 of replaceable battery 114,and each positive or anode terminal 108 is in the form of a conductivelead that extends over and is spaced above negative or cathode terminal106 a distance corresponding to the height or thickness of battery 114.The separation distance between leads 106 and 108 may be slightly lessthan the height of battery 114 wherein conductive lead 108 may beanchored with a slight spring bias to enable it to bend slightly upwardupon receiving the front end of battery 114 and provide a snug fittherewith. When battery pack 120 is fully engaged with device housing102, batteries 114 are seated between respective battery receptacleterminals 106 and 108, as best shown in FIG. 5B.

Reset contacts 110 a, 110 b are in the form of conductive pads or viaswithin PCB 104 where contact 110 a is electrically coupled to systemground and contact 110 b is electrically coupled to an input of resetcircuit 60, as shown in FIG. 1. As best shown in FIG. 2C, the height ofreset contacts 110 a, 110 b extends a distance D₁ which is slightlyhigher than the top surface of battery receptacle terminal 106 andslightly above the battery insertion plane 125 traversed by batteries114 as tray 122 is operatively coupled with device housing 102. DistanceD₁, in certain embodiments, may range from about 0.01 mm to 1.0 mm.Further, reset contacts 110 a, 110 b are laterally spaced a distance D₂from the peripheral leading edge 106 a of battery receptacle contact pad106. In certain embodiments, the reset contacts may be positionedadjacent to battery receptacle contact pad 108 in a similar manner. Ineither configuration, the separation between the reset contact pointsand the battery receptacle contact pads insulates them from each other.Distance D₂ may range from about 0.01 mm to 10 mm in certainembodiments.

In the power reset circuitry described above with respect to FIG. 1, therelative height of reset contacts 110 a, 110 b and their structuraljuxtaposition to the device's battery receptacles collectively provideand enable a power reset cycle of the present disclosure which isimplemented each time the batteries 114/battery pack 120 are inserted orremoved from device 100. Such power reset cycle is described withreference to FIGS. 3A/3B, 4A/4B and 5A/5B as well as to the graphs ofFIGS. 6A and 6B. As shown in FIGS. 3A and 3B, upon commencing insertionof batteries 114 into their corresponding battery receptacles 106, abattery 114 is slid over reset contacts 110 a, 110 b whereby the bottomor anode surface 118 of the battery physically bridges and electricallyshorts the reset contacts. At this first stage of the power reset cycle(commencing at battery position 1), the batteries 114 have yet tocontact their respective receptacles. As such, with reference to thevoltage graphs of FIGS. 6A and 6B, the reset line 80 input to dataprocessor 20 is set HI while the power line 50 input to data processor20 is set LO. Midway through battery installation, as shown in FIGS. 4Aand 4B, batteries 114 are positioned within their respective batteryreceptacle such that battery cap or anode 116 engages battery receptaclecathode 106 and battery can or cathode 118 engages battery receptacleanode 108. At this second stage of the power reset cycle (commencing atbattery position 2), as shown in FIGS. 6A and 6B, power line 50 input todata processor 20 goes HI while the reset line 80 input to dataprocessor 20 remains HI. As such, certain of the device's electronicsare electronically reset. A reset event will initialize the electroniccircuit to a known or default state, the nature of the state will dependon the circuit. During this reset stage, the device is powered byreplaceable batteries 114 which guarantees that the reset signal issensed or received by data processor 20 regardless of the state orexistence of a backup battery or large powering capacitors. Finally, asbattery pack 120 is completely advanced, as shown in FIGS. 5A and 5B,the batteries 114 moves off of reset contacts 110 a, 110 b and becomefully seated within their respective battery receptacles. At this thirdand final stage of the battery insertion power reset cycle (commencingat battery position 3), as shown in FIGS. 6A and 6B, power line 50 inputto data processor 20 remains HI while the reset line 80 input to dataprocessor 20 goes LO. The separation distance D₂ between the resetcontact points 110 a, 110 b and the battery receptacle pad 106 ensuresthat device 100 is not held in a reset mode during normal operation. Amulti-stage power reset cycle is also provided upon removal of batteries114/battery pack 120 from device 100, but with the stages occurring inreverse order from the process just described.

The subject power reset system thus operates by using a single surfaceor pole of a battery and a pair of reset contact points as anelectro-mechanical switch to trigger and cease a power cycling or resetstate of the system. In certain embodiments, no additional user actionis required to initiate such a reset. Further, in certain embodiments,no additional device housing access ports or switch receptacles arenecessary, reducing manufacturing costs and minimizing the risk ofliquid or electrostatic discharge (ESD) ingress into the device.

Certain embodiments of the present disclosure may include power cyclingan electronic device having a data processor including enabling a resetcircuit to provide a reset signal to the data processor, supplying powerto the data processor while enabling the reset circuit, disabling thereset circuit while maintaining power to the data processor, enablingthe reset circuit while maintaining power to the data processor, andremoving power to the data processor while enabling the reset circuit.

In certain embodiments, enabling the reset circuit may includeconductively grounding the reset circuit.

In certain embodiments, conductively grounding the reset circuit mayinclude positioning one pole of a battery across two reset contactpoints.

In certain embodiments, supplying power to the data processor mayinclude positioning the battery between ground and a power circuit ofthe device.

In certain embodiments, disabling the reset circuit may include removingthe battery from the two reset contact points.

Certain embodiments of the present disclosure may include an electronicdevice including a device housing that encases power cycling electroniccomponents of the electronic device comprising a printed circuit boardincluding a data processor, a power interface circuit that provides atleast one power input line to the data processor, a reset circuit thatprovides a reset signal to the data processor via a reset line, abattery receptacle terminal configured to receive a battery packincluding at least one cathode terminal, at least one anode terminal,and at least one reset pad electrically coupled to an input of the resetcircuit, and a battery pack including a housing and at least one batteryretained in the housing and positioned between at least one batterybetween the at least one cathode terminal and the at least one anodeterminal, the battery configured as the supply voltage of the electronicdevice, wherein the reset circuit includes a reset switch positionedbetween the reset circuit and system ground.

In certain embodiments, the data processor may include a microprocessor.

In certain embodiments, separation distance between the at least onecathode terminal and the at least one anode terminal may be less thanthe thickness of the at least one battery.

In certain embodiments, at least one anode terminal may be anchored witha spring bias that enables a bending of the at least one anode terminalupon receipt of the at least one battery between the at least onecathode terminal and the at least one anode terminal.

In certain embodiments, at least one reset pad may include a first resetpad electrically coupled to device ground and a second reset padelectrically coupled to an input of the reset circuit.

In certain embodiments, a height of the at least one reset pad may begreater than a top surface of the at least one cathode terminal.

In certain embodiments, the height of the at least one reset pad may bein a range of 0.01 mm to 1.0 mm.

In certain embodiments, at least one battery may be a replaceablebattery.

In certain embodiments, the battery pack may be configured to engagewith the battery receptacle terminal in a sliding or snap-fit manner.

In certain embodiments, at least one reset pad may be laterally spacedfrom a leading peripheral edge of the at least one cathode terminal.

In certain embodiments, the lateral spacing of the at least one resetpad from the leading peripheral edge of the at least one cathodeterminal may be in a range of 0.01 mm to 10 mm.

Certain embodiments of the present disclosure may include power cyclingan electronic device having a data processor including receiving, at oneor more reset contact, an electrical short from at least one battery,receiving, at one or more data processors, a first voltage input signalfrom one or more reset lines that is HI, receiving, at the one or moredata processors, a second voltage input signal from one or more powerlines that is LO, receiving, at the one or more data processors, a thirdvoltage input signal from the one or more power lines that is HI,determining, at the one or more data processors, that the first voltageinput signal from the one or more reset lines remains HI, receiving, atthe one or more data processors, a fourth voltage input signal from theone or more reset lines that is LO, and determining, at the one or moredata processors, that the third voltage input signal from the one ormore power lines remains HI.

While the present disclosure has been described with reference to thespecific embodiments thereof, it should be understood by those skilledin the art that various changes may be made and equivalents may besubstituted without departing from the true spirit and scope of thedisclosure. In addition, many modifications may be made to adapt aparticular situation, material, composition of matter, process, processstep or steps, to the objective, spirit and scope of the presentdisclosure. All such modifications are intended to be within the scopeof the claims appended hereto.

What is claimed is:
 1. A method of power cycling an electronic devicehaving a data processor, the method comprising: enabling a reset circuitto provide a reset signal to a data processor of an electronic device toinitiate a first power reset cycle; supplying power to the dataprocessor while enabling the reset circuit to initialize the electronicdevice to a known state; disabling the reset circuit while maintainingpower to the data processor to operate the electronic device and tocomplete the first power reset cycle; enabling the reset circuit whilemaintaining power to the data processor to initiate a second power resetcycle; removing power to the data processor while the reset circuit isenabled to perform the second power reset cycle; and disabling the resetcircuit to complete the second power reset cycle.
 2. The method of claim1, wherein the enabling the reset circuit comprises conductivelygrounding the reset circuit.
 3. The method of claim 2, wherein theconductively grounding the reset circuit comprises positioning one poleof a battery across two reset contact points.
 4. The method of claim 3,wherein the supplying power to the data processor comprises positioningthe battery between ground and a power circuit of the device.
 5. Themethod of claim 4, wherein the disabling the reset circuit includesremoving the battery from the two reset contact points.
 6. An electronicdevice including a device housing that encases power cycling electroniccomponents of the electronic device, comprising: a printed circuit boardincluding a data processor; a power interface circuit that provides atleast one power input line to the data processor; a reset circuit thatprovides a reset signal to the data processor via a reset line, thereset circuit including a reset switch comprising at least one reset padprovided on the printed circuit board, the reset circuit configured toinitiate a power reset cycle of the electronic device; a batteryreceptacle configured to receive a battery pack including at least onecathode terminal and at least one anode terminal; and the battery packincluding a housing and at least one battery retained in the housing andpositioned between the at least one cathode terminal and the at leastone anode terminal, the battery configured to provide power to theelectronic device, wherein the insertion of the battery pack into thebattery receptacle triggers the reset circuit to initiate the powerreset cycle of the electronic device, to initialize the electronicdevice to a known state, and to complete the initiated power resetcycle.
 7. The electronic device of claim 6, wherein the data processorincludes a microprocessor.
 8. The electronic device of claim 6, whereina separation distance between the at least one cathode terminal and theat least one anode terminal is less than a thickness of the at least onebattery.
 9. The electronic device of claim 6, wherein the at least oneanode terminal is anchored with a spring bias that enables a bending ofthe at least one anode terminal upon receipt of the at least one batterybetween the at least one cathode terminal and the at least one anodeterminal.
 10. The electronic device of claim 6, wherein the at least onereset pad includes a first reset pad electrically coupled to deviceground and a second reset pad electrically coupled to an input of thereset circuit.
 11. The electronic device of claim 6, wherein a height ofthe at least one reset pad is greater than a top surface of the at leastone cathode terminal.
 12. The electronic device of claim 11, wherein theheight of the at least one reset pad is in a range of 0.01 mm to 1.0 mm.13. The electronic device of claim 6, wherein the at least one batteryis a replaceable battery.
 14. The electronic device of claim 6, whereinthe battery pack is configured to engage with the battery receptacle ina sliding or snap-fit manner.
 15. The electronic device of claim 6,wherein the at least one reset pad is laterally spaced from a leadingperipheral edge of the at least one cathode terminal.
 16. The electronicdevice of claim 15, wherein the lateral spacing of the at least onereset pad from the leading peripheral edge of the at least one cathodeterminal is in a range of 0.01 mm to 10 mm.
 17. A method of powercycling an electronic device having a data processor, the methodcomprising: receiving, at one or more reset contact points, anelectrical short from at least one battery by positioning one pole ofthe battery over the one or more reset contact points; receiving, at oneor more data processors, a first voltage input signal from one or morereset lines that is HI to initiate a power reset cycle of an electronicdevice; receiving, at the one or more data processors, a second voltageinput signal from one or more power lines that is LO; receiving, at theone or more data processors, a third voltage input signal from the oneor more power lines that is HI to initialize the electronic device to aknown state; determining, at the one or more data processors, that thefirst voltage input signal from the one or more reset lines remains HI;receiving, at the one or more data processors, a fourth voltage inputsignal from the one or more reset lines that is LO to complete the powerreset cycle; and determining, at the one or more data processors, thatthe third voltage input signal from the one or more power lines remainsHI to operate the electronic device.